synopsys constrain

Synopsis Constraints

Synopsis Constraints .

The following are some of useful Synopsis Constraints.

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#### Portion to Edit
#### Variables clock1_name is the Clock name, clock1_period is the Clock period,
#### clock1_period_half is the half of the clock period
#### set clock1_name <clock1_name>
#### set clock1_period <clock1_period>
#### set clock1_period_half [expr $clock1_period / 2]
#### set clock1_period_onetenth [expr $clock1_period / 10]
#### set clock1_period_onetwenth [expr $clock1_period / 20]
#### set clock1_latency <clock1_latency_number>
#### set CTS_clock1_skew <CTS_clock1_skew_number>
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#### Source the .synopsys_dc_setup file, File which has all the library settings
source .synopsys_dc_setup
#### Read the rtl files
read_verilog <RTL file name>
### Similar way read all the RTL files
### Specify the Top-level file name
current_design <top-level module name>
#### Link the design
link
#### Uniquify the design, for designs with multiple instantiation
uniquify
#### Design Constraints following....
####Specify the Clocks in the Design ######
#### Example for one Clock in the Design named clock1
create_clock -period $clock1_period -waveform [list 0 $clock1_period_half ] -name $clock1_name <specify the location of the node where clock need to be generated>
set_clock_skew -ideal -uncertainty $CTS_clock1_skew $clock1_name
set_clock_transition 0.3 $clock1_name
set_clock_latency $clock1_latency_number $clock1_name
set_dont_touch_network $clock1_name
#### Generate the same list of constraints for all the clocks in the design
#### Generate the False and Multi-cycle paths in the design as Timing Exceptions for the tool.
#### False And Multi-cycle paths are purely Design Specific.
#set_false_path -from <Source > -to <Destination> -setup
#set_false_path -from <Source > -to <Destination> -hold
#set_multicycle_path <no of cycles>  -from <source> -to <destination>


##### Steps to constrain the inputs/outputs and the design
set_input_transition $clock1_period_onetenth [all_inputs]
set_max_transition $clock1_period_onetwenth $current_design
#### Specify the wire-load model
set auto_wire_load_selection true    ### Tool automatically selects the wire-load model
#### Create virtual clocks to constrain the ports.To understand concept behind the virtual clocks
#### Check out the ASIC FAQ's column.
#### To constrain inputs
set_input_delay <input delay value>  -clock <with respect to virtual clock>  <input_port1>
### Similar way define for all the inputs and w.r.t virtual clocks
#### To constrain out-puts
set_output_delay <output delay value>  -clock <with virtual clock>  <output_port1>
### Similar way define for all the outputs and w.r.t virtual clocks

### To constrain purely combinational paths
set_max_delay <specify delay values> -from <source path> -to <destination path>
### For the high fanout nets for which tree will be built and to get away from false loading violation
set_ideal_net <reset_name>
set_ideal_net <scan_enable_name>
### In-order to constrain specific paths passing through the muxes, for example for the tool to
### concentrate on the functional-paths , specify case_analysis for functional paths.
set_case_analysis <case value 0/1> <Mux/Bi-furcating paths>
#### If the design requirement is for area critical designs
set_max_area 0
#### To prevent the tool from optimizing
#set_dont_touch <area to be dont-touched>
####Mapping the RTL specific to the Targetted Technology Library
#### The command means to map it , with scannable flop's, with high optimization possible,
#### Area optimized for non-critical-paths as-well-as boundary paths optimized.
compile -scan -map_effort high -area_effort high -boundary_optimization
#### Save the database
write -f db -h -o <design_name.db>
#### Set some variables for proper saving of verilog netlist file
set verilogout_no_tri true
set bus_naming_style [format "%s%s" "%s\[" "%d\"]
write -f verilog -h -o <design_name.v>
### Save the Used SDC(Synopsys Design Constraints file>
write_sdc <design_name.sdc>
###Report Generation
report_constraints -all_violators -verbose  ### Command to report all the violations
report_area  ### command to report the design area
report_reference ### command to report the design details as per the sub-blocks
### A very powerful command to know the quality of the design constraints
check_design   ###Command to know the design <for example flops which are not getting clocks, ports which are not constrained>
#### Now, let us know the Test Part of the Design
set test_default_period 100
set test_default_delay 5
set test_default_bidir_delay 30
set test_default_strobe 35
set test_default_strobe_width 0
#### Specify that there is no scan-chain present in the design
set_scan_configuration -existing_scan false
#### specify whether clock mixing is allowed or not while scanstitching
set_scan_configuration -clock_mixing no_mix
#### specify the style of flip-flop
set_scan_configuration -style multiplexed_flip_flop
#### Specify the scanchain methodology whether full-scan or partial scan
set_scan_configuration -methodology full_scan
#### Specify the longest chain length according to the tester memory
set_scan_configuration -longest_chain_length 200
#### Specify the scan-enable signal
set_scan_signal test_scan_enable -port <design_scan enable port name>
#### Specify a case analysis value for to the tool to be in the scan-mode while scan-stitching
set_test_hold <value either 0/1> <design scan-mode port name>
#### Specify the designs for which scan-stitching is not required
set_scan_element false [get_designs <sub design_name>
#### Specify the scan-in and scan-out port of the design to the tool
set_scan_signal test_scan_in -port [get_ports <design scan_port input>
set_scan_signal test_scan_out -port [get_ports <design scan_port out-put>
#### specify the test-clock in the design
create_test_clock < clock_name> -period < specify period numeric>  -waveform {rise-edge fall-edge}
#### run the check-test to know the design violations w.r.t. test <
check_test -verbose
##### command to insert scan
insert_scan -map_effort high
#### Report generation
report_test -scan_path   ### command to list all the scan-chains
#### Save the database
write -f db -h -o <design_name_scan.db>
#### Set some variables for proper saving of verilog netlist file
set verilogout_no_tri true
set bus_naming_style [format "%s%s" "%s\[" "%d\"]
write -f verilog -h -o <design_name_scan.v>
###Report Generation after scan-insertion
report_constraints -all_violators -verbose  ### Command to report all the violations
report_area  ### command to report the design area
report_reference ### command to report the design details as per the sub-blocks