cadance command

CADENCE COMMAND LINE OPTIONS

CADENCE COMMAND LINE OPTIONS.

Multiple Step mode uses the ncvlog and ncelab commands to compile and elaborate your design; Single Step mode uses the ncverilog command.

COMMANDS FOR MUTIPLE STEP MODE:

For explaining the commands design file assumed is - tb_spi_ifc_top.v, and all the commands are given in italic.

Creation of new project:

nclaunch -new

Creates work library (INCA_libs/worklib), cds.lib, and nclaunch.key.
Before you can simulate your design, you must compile and elaborate it.

Compile:

Compiling the design produces an internal representation for each HDL design unit in the source files.
ncvlog -work worklib -cdslib cds.lib -logfile ncvlog.log (-logfile ncvlog.log -apeend_log) (-nolog) -errormax 15 -update -linedebug -status tb_spi_ifc_top.v
-status option gives following information

ncvlog: Memory Usage - 6.4M program + 4.9M data = 11.2M total
ncvlog: CPU Usage - 0.0s system + 0.1s user = 0.1s total (0.1s, 44.1% cpu)

Elaborate:

Elaborating the design constructs a design hierarchy based on the instantiation and configuration information in the design, establishes signal connectivity, and computes initial values for all objects in the design.
ncelab -Message -work worklib -cdslib cds.lib -logfile ncelab.log -errormax 15 -access +wc -status worklib.tb_spi_ifc_top:module

Simulate - run mode ‘Graphical UI’

ncsim -Message -gui -cdslib cds.lib -logfile ncsim.log -errormax 15 -licqueue -status worklib.tb_spi_ifc_top:module
run

Simulate - run mode ‘Batch’

ncsim -Message -batch -cdslib cds.lib -logfile ncsim.log -errormax 15 -licqueue -status worklib.tb_spi_ifc_top:module
-licqueue option puts the simulation in wait mode till we get the license.

Dumping the waveform file for debugging

ncsim -Message -batch -cdslib cds.lib -logfile ncsim.log -input run.cmd -errormax 15 -licqueue -status worklib.tb_spi_ifc_top:module
Contents of run.cmd file
database -open waves -into waves.shm -default
probe -create -shm -all -variables -depth all
run
Options for code coverage:

For code coverage elaboration and simulation options are different and following are the commands,
Instrument the design by passing the coverage configuration file named covfile.cf during the elaboration,
ncelab -Message -covfile covfile.cf -work worklib -cdslib cds.lib -logfile ncelab.log -errormax 15 -access +wc -status worklib.tb_spi_ifc_top:module
Simulate the design by passing the simulation input file named sim_code.tcl,
ncsim -Message -input sim_code.tcl -cdslib cds.lib -logfile ncsim.log -errormax 15 -licqueue -status worklib.tb_spi_ifc_top:module

Contents of file covfile.cf:

select_coverage -block -expr -toggle -instance *…
select_fsm -module *
set_hit_count_limit 4
set_assign_scoring
set_glitch_strobe 100 ps
set_toggle_strobe 100 ps

Particular instances and modules of interest for coverage can be specified instead of *… and * respectively.

Contents of sim_code.tcl
coverage -setup -dut tb_spi_ifc_top.u_spi_wb
coverage -setup -testname mic_arb1
coverage -code -score b:e
coverage -code -database -local_db mic_arb1.cov
coverage -fsm -database -local_db mic_arb1.fsm
coverage -toggle -database -local_db mic.mst
run
exit

After simulation, directory named “cov_work” will be created with following files (coverage data),

spi_wb.dgn and mic_arb1.cov è Block and expression coverage
mic.mst and mic_arb1.tog è Toggle coverage
mic_arb1.fsm è FSM coverage

Invoking the reporting tool to analyze the coverage data,

ictr -g

and load above files to analyze the coverage data.
Above commands give block, expression, toggle and FSM coverage. For functional coverage assertions should be included in the design and is not covered by above commands.
Some time back in cadence demo/presentation, we were discussing about ‘-access +rwc’ in elaboration of design, and Tutorial PDF says
“This option provides full access (read, write, and connectivity access) to simulation objects so that you can probe objects and scopes to a simulation database and debug the design”
I encountered one example of accessing simulation object and wanted to share with all you folks,
During the simulation we can force/deposit value to any signal (deposit is also like force except time can be controlled),
force tb_spi_ifc_top.boot_load = 1‘h1;
deposit tb_spi_ifc_top.boot_load = 1‘h1 -after 100ns -absolute
(Can also be issued using ‘simulation’ menu of simvision)
This is nothing but accessing the simulation object, for this we need the access to be enabled.