| Logic Circuits |
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| | Boolean algebra is ideal for expressing the behavior of logic circuits. |
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| | A circuit can be expressed as a logic design and implemented as a collection of individual connected logic gates. |
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|  | Fixed Logic Systems |
| | A fixed logic system has two possible choices for representing true and false. |
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|  | Positive Logic |
| | In a positive logic system, a high voltage is used to represent logical true (1), and a low voltage for a logical false (0). |
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|  | Negative Logic |
| | In a negative logic system, a low voltage is used to represent logical true (1), and a high voltage for a logical false (0). |
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| | In positive logic circuits it is normal to use +5V for true and 0V for false. |
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|  | Switching Circuits |
| | The abstract logic described previously can be implemented as an actual circuit. Switches are left open for logic 0 and closed for logic 1. |
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|  | Two variable AND circuit X.Y |
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| |  |
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|  | Two variable OR circuit X + Y |
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| |  |
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|  | Four variable circuit U.V.(X + Y) |
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| |  |
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|  | Truth Table |
| | A truth table is a means for describing how a logic circuit's output depends on the logic levels present at the circuit's inputs. |
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| | In the following twos-inputs logic circuit, the table lists all possible combinations of logic levels present at inputs X and Y along with the corresponding output level F. |
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| |  |
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X | Y | F = X*Y |
0 | 0 | 0 |
0 | 1 | 0 |
1 | 0 | 0 |
1 | 1 | 1 |
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| | When either input X AND Y is 1, the output F is 1. Therefore the "?" in the box is an AND gate. |
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